Wave Pipelining: Theory and CMOS Implementation Book

	List of Figures
	List of Tables
	Preface
1	Introduction and Motivation	1
1.1	Wave Pipelining	2
1.2	History	6
1.3	Designing Wave Pipelined Circuits	8
1.4	Organization	10
2	Clock Period Constraints: Single Stage Systems	13
2.2	System Model	16
2.3	Constraints for Correct Clocking	19
2.4	Minimizing the Clock Period	30
2.5	The Parameter k	33
2.6	Special Cases	39
3	Clock Period Constraints: Multiple Stage Systems	45
3.2	System Model	46
3.3	Constraints for Correct Clocking	48
3.4	Example	57
4	Exact Timing Analysis	61
4.2	Motivation and Justification	63
4.3	Complexity of Problem	76
4.4	Notation and Model	78
4.5	Basic Algorithm Development	83
5	Exact Timing Analysis: Algorithm	87
5.2	Algorithm Strategy	88
5.3	Calculation of Output Responses	88
5.4	Verification of Output Responses	92
5.5	Detection of Components	102
5.6	Vector Reporting	103
5.7	Implementation	104
5.8	Limitations and Extensions	113
6	Practical Considerations in Wave Pipelining	125
6.1	Architecture Choice	126
6.2	Path Delay Variation	127
6.3	Circuit Choice	128
6.4	Parametric Variations due to Manufacturing and Environmental Factors	132
6.5	Clock Distribution and Physical Layout	134
6.6	Technology Scaling	136
7	Design Examples	139
7.2	Parallel-Carry Adder	140
7.3	Sampler	160
8	Conclusions	183
	A Example Model File	187
	B Calculation of Tolerance of Parametric Variations	191
	References	195
	Index	205