Hot-Carrier Reliability Of Mos Vlsi Circuits Book

	Preface
	Acknowledgements
1	Introduction	1
1.1	The Concept of IC Reliability	1
1.2	Design-for-Reliability	4
1.3	VLSI Reliability Problems	6
1.4	Gradual Degradation versus Catastrophic Failures	7
1.5	Hot-Carrier Effects	9
2	Oxide Degradation Mechanisms in MOS Transistors	15
2.2	MOS Transistor : A Qualitative View	16
2.3	The Nature of Gate Oxide Damage in MOSFETs	19
2.4	Injection of Hot Carriers into Gate Oxide	21
2.5	Oxide Traps and Charge Trapping	31
2.6	Interface Trap Generation	34
2.7	Bias Dependence of Degradation Mechanisms	36
2.8	Degradation under Dynamic Operating Conditions	39
2.9	Effects of Hot-Carrier Damage on Device Characteristics	43
2.10	Hot-Carrier Induced Degradation of pMOS Transistors	47
3	Modeling of Degradation Mechanisms	55
3.2	Quasi-Elastic Scattering Current Model	56
3.3	Charge (Electron) Trapping Model	64
3.4	Impact Ionization Current Model	66
3.5	Interface Trap Generation Model	67
3.6	Trap Generation under Dynamic Operating Conditions	71
4	Modeling of Damaged MOSFETs	77
4.2	Representation of Hot-Carrier Induced Oxide Damage	78
4.3	Two-Dimensional Modeling of Damaged MOSFETs	80
4.4	Empirical One-Dimensional Modeling	83
4.5	An Analytical Damaged MOSFET Model	89
4.6	Consideration of Channel Velocity Limitations	101
4.7	Pseudo Two-Dimensional Modeling of Damaged MOSFETs	103
4.8	Table-Based Modeling Approaches	104
5	Transistor-Level Simulation for Circuit Reliability	111
5.2	Review of Circuit Reliability Simulation Tools	112
5.3	Circuit Reliability Simulation Using iSMILE : A Case Study	119
5.4	Circuit Simulation Examples	124
5.5	Evaluation of the Simulation Algorithm	133
5.6	Identification of Critical Devices	136
6	Fast Timing Simulation for Circuit Reliability	143
6.2	ILLIADS-R : A Fast Timing and Reliability Simulator	144
6.3	Fast Dynamic Reliability Simulation	148
6.4	Circuit Simulation Examples with ILLIADS-R	155
6.5	iDSIM2 : Hierarchical Circuit Reliability Simulation	159
7	Macromodeling of Hot-Carrier Induced Degradation in MOS Circuits	165
7.2	Macromodel Development : Starting Assumptions	166
7.3	Degradation Macromodel for CMOS Inverters	167
7.4	Degradation Macromodel for nMOS Pass Gates	173
7.5	Application of the Macromodel to Inverter Chain Circuits	179
7.6	Application of the Macromodel to CMOS Logic Circuits	186
8	Circuit Design for Reliability	191
8.2	Device-Level Measures	193
8.3	Circuit-Level Measures	199
8.4	Rule-Based Diagnosis of Circuit Reliability	203
	Index	209