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System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors | 1 | |
Ramp Up/Down Functional Unit to Reduce Step Power | 13 | |
An Adaptive Issue Queue for Reduced Power at High Performance | 25 | |
Dynamic Memory Oriented Transformation in the MPEG4 IM1-Player on a Low Power Platform | 40 | |
Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering | 51 | |
Compiler-Directed Dynamic Frequency and Voltage Scheduling | 65 | |
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power | 82 | |
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors | 97 | |
TEM[superscript 2]P[superscript 2]EST: A Thermal Enabled Multi-model Power/Performance ESTimator | 112 | |
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor | 126 | |
A Comparison of Two Architectural Power Models | 137 | |
Author Index | 153 |
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Add Power-Aware Computer Systems, This book constitutes the thoroughly refereed post-proceedings of the First International Workshop on Power-Aware Computer Systems, PACS 2000, held in Cambridge, MA, USA, in November 2000. The 11 revised full papers presented were carefully reviewed, , Power-Aware Computer Systems to the inventory that you are selling on WonderClubX
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Add Power-Aware Computer Systems, This book constitutes the thoroughly refereed post-proceedings of the First International Workshop on Power-Aware Computer Systems, PACS 2000, held in Cambridge, MA, USA, in November 2000. The 11 revised full papers presented were carefully reviewed, , Power-Aware Computer Systems to your collection on WonderClub |