The Best of ICCAD Book

	Foreword
	Preface
	Formal Methods for Functional Verification	3
	Automating the Diagnosis and the Rectification of Design Errors with PRIAM	17
	Functional Comparison of Logic Designs for VLSI Circuits	29
	A Unified Framework for the Formal Verification of Sequential Circuits	39
	Dynamic Variable Ordering for Ordered Binary Decision Diagrams	51
	Verification of Large Synthesized Designs	65
	GRASP - A New Search Algorithm for Satisfiability	73
	System Design and Analysis Overview	93
	An Efficient Microcode-Compiler for Custom DSP-Processors	107
	HYPER-LP: A System for Power Minimization Using Architectural Transformations	117
	Power Analysis of Embedded Software: First Step Towards Software Power Minimization	129
	A Methodology for Correct-by-Construction Latency Insensitive Design	143
	Exploring Performance Tradeoffs for Clustered VLIV ASIPs	159
	Logic Synthesis Overview	181
	Multiple-Level Logic Optimization System
	Exact Minimization of Multiple-Valued Functions for PLA Optimization	205
	Improved Logic Optimization Using Global-Flow Analysis	217
	A Method for Concurrent Decomposition and Factorization of Boolean Expressions	227
	An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs	235
	Logic Decomposition during Technology Mapping	249
	Highlights in Analog and Digital Circuit Design and Synthesis at ICCAD	269
	An Interactive Device Characterization and Model Development System	285
	TILOS: A Posynomial Programming Approach to Transistor Sizing	295
	SPECS2: An Integrated Circuit Timing Simulator	303
	Automatic Synthesis of Operational Amplifiers based on Analytic Circuit Models	313
	Analog Circuit Synthesis for Performance in OASYS	325
	Extraction of Gate-Level Models from Transistor Circuits by Four-Valued Symbolic Analysis	337
	Optimization of Custom MOS Circuits by Transistor Sizing	347
	Highlights in Physical Simulation and Analysis at ICCAD	367
	Nonlinear Simulation in the Frequency-Domain	383
	Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation	393
	Efficient Techniques for Inductance Extraction of Complex 3-D Geometrics	403
	Time-Domain Non-Monte Carlo Noise Simulation for Nonlinear Dynamic Circuits with Arbitrary Excitations	413
	PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm	433
	Circuit Noise Evaluation by Pade Approximation Based Model-Reduction Techniques	451
	Physical Design Overview	467
	Floorplan Design Using Annealing	479
	GOALIE: A Space-Efficient System for VLSI Artwork Analysis	489
	Gordian: A New Global Optimization/Rectangle Dissection Method for Cell Placement	499
	Exact Zero Skew	509
	Efficient Network Flow Based Min-Cut Balanced Partitioning	521
	Rectangle-Packing-Based Module Placement	535
	Timing, Test and Manufacturing Overview	551
	A Methodology for Worst Case Design of Integrated Circuits	563
	Timing Analysis using Functional Relationships	567
	On the Design of Robust Multiple Fault Testable CMOS Combinational Logic Circuits	575
	Circuit Optimization Driven by Worst-Case Distances	585
	Verifying Clock Schedules	597
	Efficient Implementation of Retiming	615
	A Cadence Perspective on ICCAD	633
	ICCAD and Fujitsu	639
	ICCAD's Impact in IBM	645
	Magma and ICCAD	653
	Designers Face Critical Challenges and Discontinuities of Analog/Mixed Signal Design and Physical Verification	659
	NEC and ICCAD - EDA partners in success	663
	The Strong Mutual Impact between Phillips Research and the ICCAD	675
	Contributions from the "Best of ICCAD" to Synopsys	683
	ICCAD and Xilinx	689
	Index	697
	Author Index	705
	Reference Index	707