Wonder Club world wonders pyramid logo
×

Memory Technology, Design and Testing Book

Memory Technology, Design and Testing
Memory Technology, Design and Testing, , Memory Technology, Design and Testing has a rating of 3 stars
   2 Ratings
X
Memory Technology, Design and Testing, , Memory Technology, Design and Testing
3 out of 5 stars based on 2 reviews
5
0 %
4
0 %
3
100 %
2
0 %
1
0 %
Digital Copy
PDF format
1 available   for $211.75
Original Magazine
Physical Format

Sold Out

  • Memory Technology, Design and Testing
  • Written by author Institute of Electrical and Elec
  • Published by IEEE Computer Society Press, 7/28/1995
Buy Digital  USD$211.75

WonderClub View Cart Button

WonderClub Add to Inventory Button
WonderClub Add to Wishlist Button
WonderClub Add to Collection Button

Book Categories

Authors

Message from the General Chair
Message from the Program Chair
Technical Program Committee
Keynote Speech: Challenges in Memory - Logic Integration 2
Modeling Application Specific Memories 10
A Modeling and Circuit Reduction Methodology for Circuit Simulation of DRAM Circuits 15
A New Serial Sensing Approach for Multistorage Non-Volatile Memories 21
Technology and Layout Related Testing 28
Embedded RAM Testing 29
A Bipartite, Differential I[subscript DDQ] Testable Static RAM Design 36
CMOS SRAM Test Based on Quiescent Supply Current in Write Operation 42
Detection of Faults in ECL Storage Elements 48
Automatic Computation of Test Length for Pseudo-Random Memory Tests 56
An Efficient Test Method for Embedded Multi-port RAM with BIST Circuitry 62
A 5 Gb/s 9-Port Application Specific SRAM with Built-In Self Test 68
AN 2 Cycle 1Mbit 4 Way Set Associative 4 Way Interleave Multi-processor L2 Directory with Array Access/Cycle 2.5 nsec 76
Optimization of Memory Organization and Hierarchy for Decreased Size and Power in Video and Image Processing Systems 82
Logic-Enhanced Memories for Data-Intensive Processing 88
The Rambus Memory System 94
Performance in Real-Time Main-Memory Databases 97
Gallium Arsenide MESFET Memory Architectures 103
Yield and Cost Estimation for a CAM÷Based Parallel Processor 110
Deterministic Tests for Detecting Scrambled Pattern-Sensitive Faults in RAMs 117
Composition of Multiple Faults in RAMs 123
Author Index 129


Login

  |  

Complaints

  |  

Blog

  |  

Games

  |  

Digital Media

  |  

Souls

  |  

Obituary

  |  

Contact Us

  |  

FAQ

CAN'T FIND WHAT YOU'RE LOOKING FOR? CLICK HERE!!!

X
WonderClub Home

This item is in your Wish List

Memory Technology, Design and Testing, , Memory Technology, Design and Testing

X
WonderClub Home

This item is in your Collection

Memory Technology, Design and Testing, , Memory Technology, Design and Testing

Memory Technology, Design and Testing

X
WonderClub Home

This Item is in Your Inventory

Memory Technology, Design and Testing, , Memory Technology, Design and Testing

Memory Technology, Design and Testing

WonderClub Home

You must be logged in to review the products

E-mail address:

Password: