High-Level Power Analysis and Optimization Book

	List of Figures
	List of Tables
	Preface
1	Introduction	1
1.1	Low power design	2
1.2	Design abstraction and levels of the design hierarchy	5
1.3	Benefits of high-level power analysis and optimization	12
1.4	Book overview	15
2	Background	17
2.1	Sources of power consumption	18
2.2	Methods for reducing power and energy consumption	22
2.3	High-level design techniques	25
2.4	High-level synthesis application domains	33
3	Architecture-Level Power Estimation	37
3.1	Analytical power models	38
3.2	Characterization based activity and power macromodels	43
3.3	Power and switching activity estimation techniques for control logic	67
3.4	Conclusions	78
4	Power Management	81
4.1	Clock-based power management: Gated and multiple clocks	82
4.2	Pre-computation	93
4.3	Scheduling to enable power management	95
4.4	Operand isolation	97
4.5	Power management through constrained register sharing	102
4.6	Controller-based power management	107
4.7	Conclusions	114
5	High-Level Synthesis for Low Power	115
5.1	Behavioral transformations	116
5.2	Module selection	126
5.3	Resource sharing	129
5.4	Scheduling	135
5.5	Supply voltage vs. switched capacitance trade-offs	139
5.6	Optimizing memory power consumption during high-level synthesis	142
5.7	Reducing glitching power consumption during high-level design	145
5.8	Conclusions	153
6	Conclusions and Future Work	155
	References	159
	Index	173