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Book Categories |
Preface | ||
Pt. 1 | Evolvable Hardware and GA | |
Ch. 1 | Automated design synthesis and partitioning for adaptive reconfigurable hardware | 3 |
Ch. 2 | High-performance hardware design and implementation of genetic algorithms | 53 |
Pt. 2 | Fuzzy Logic Hardware Implementations | |
Ch. 3 | Hardware implementation of intelligent systems | 91 |
Ch. 4 | High performance fuzzy processors | 121 |
Ch. 5 | A digital fuzzy processor for fuzzy-rule-based systems | 147 |
Pt. 3 | Neural Networks Hardware Implementations | |
Ch. 6 | Optimum multiuser detection for CDMA system using the mean field annealing neural network | 167 |
Ch. 7 | Analog VLSI hardware implementation of a supervised learning algorithm | 193 |
Ch. 8 | pRAM: the probabilistic RAM neural processor | 219 |
Pt. 4 | Algorithms for Parallel Machines | |
Ch. 9 | Parallel subgraph matching on a hierarchical interconnection network | 245 |
About the editors | 277 | |
Index of terms | 281 |
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