Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Book

	Architectural Challenges for the Next Decade Integrated Platforms	1
	Analysis of High-Speed Logic Families	2
	Low-Voltage, Double-Edge-Triggered Flip Flop	11
	A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems	21
	State Encoding for Low-Power FSMs in FPGA	31
	Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies	41
	A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates	51
	CMOS Gate Sizing under Delay Constraint	60
	Process Characterization for Low VTH and Low Power Design	70
	Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results	80
	Effects of Temperature in Deep-Submicron Global Interconnect Optimization	90
	Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits	101
	Estimation of Crosstalk Noise for On-Chip Buses	111
	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization	121
	Interconnect Driven Low Power High-Level Synthesis	131
	Bridging Clock Domains by Synchronizing the Mice in the Mousetrap	141
	Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization	151
	New GALS Technique for Datapath Architectures	161
	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders	171
	Statistic Implementation of QDI Asynchronous Primitives	181
	The Emergency of Design for Energy Efficiency: An EDA Perspective	192
	The Most Complete Mixed-Signal Simulation Solution with ADVance MS	193
	Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips	194
	Power Management in Synopsys Galaxy Design Platform	195
	Open Multimedia Platform for Next-Generation Mobile Devices	196
	Statistical Power Estimation of Behavioral Descriptions
	A Statistic Power Model for Non-synthetic RTL Operators	208
	Energy Efficient Register Renaming	219
	Stand-by Power Reduction for Storage Circuits	229
	A Unified Framework for Power-Aware Design of Embedded Systems	239
	A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems	249
	High Level Area and Current Estimation	259
	Switching Activity Estimation in Non-linear Architectures	269
	Instruction Level Energy Modeling for Pipelined Processors	279
	Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level	289
	An Adiabatic Charge Pump Based Charge Recycling Design Style	299
	Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing	309
	Low Power Response Time Accelarator with Full Resolution for LCD Panel	319
	Memory Compaction and Power Optimization for Wavelet-Based Coders	328
	Design Space Exploration and Trade-Offs in Analog Amplifier Design	338
	Power and Timing Driven Physical Design Automation	348
	Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks	358
	Remote Power Control of Wireless Network Interfaces	369
	Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders	379
	A Fully Digital Numerical-Controlled-Oscillator	389
	Energy Optimization of High-Performance Circuits	399
	Instruction Buffering Exploration for Low Energy Embedded Processors	409
	Power-Aware Branch Predictor Update for High-Performance Processors	420
	Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms	430
	High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder	440
	Metric Defination for Circuit Speed Optimization	451
	Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies	461
	An Asynchronous Viterbi Decoder for Low-Power Applications	471
	Analysis of the Contribution of Interconnect Effect in the Energy Dissipation of VLSI Circuits	481
	A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application	491
	Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits	501
	A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages	511
	Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus	520
	Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction	530
	A Bottom-Up Approach to On-Chip Signal Integrity	540
	Advanced Cell Medeling Techniques Based on Polynomial Expressions	550
	RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches	559
	Data Dependences Critical Path Evaluation at C/C++ System Level Description	569
	A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements	580
	Consideration of Control System and Memory Contributions in Pratical Resource-Constrained Scheduling for Low Power	590
	Low Power Cache with Successive Tag Comparison Algorithm	599
	FPGA Architecture Design and Toolset for Logic Implementation	607
	Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis	617
	Author Index	629