Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits Book

PREFACE.

CHAPTER 1 – INTRODUCTION. 1 Problem Overview: The Design Gap. 1.1 Evolution of the semiconductor industry. 1.2 The design gap. 1.2.1 Time-to-market. 1.2.2 Design complexity. 1.3 Analog design automation. 2 Problem definition. 2.1 Hierarchy, abstraction, and views. 2.2 The AMS design flow. 3 Summary.

CHAPTER 2 - A REUSE-BASED DESIGN FRAMEWORK FOR ANALOG ICs. 1 Design automation. 1.1 Preliminary definitions. 1.2 The two sides of automation. 1.2.1 Knowledge-based synthesis . 1.2.2 Optimization-based synthesis. 1.2.3 Quality metrics for analog synthesis . 1.3 Knowledge versus optimization-based synthesis. 2. Circuit reuse. 2.1 Preliminary definitions. 2.2. Digital design reuse. 2.3 Analog design reuse. 2.4 Other approaches to analog reuse. 3 The reuse-based design framework. 3.1 The analog reusable block. 3.2 The design reuse flow. 3.2.1 Adopted synthesis approaches. 3.2.2 The top-down path. 3.2.3 The bottom-up path. 3.2.4 The role of the analog reusable block. 3.3 The design for reusability methodology. 4 Summary.

CHAPTER 3 - THE ANALOG REUSABLE BLOCK: BEHAVIORAL FACET. 1 Introduction: Why behavioral descriptions? 1.1 Analog behavioral modeling taxonomy. 2 Facing design reuse. 2.1 The design reuse flow: top-down electrical synthesis. 2.2 The design reuse flow: bottom-up verification. 2.3 Characteristics of the behavioral facet of the AMS reusable block. 3 Case study: a quadrature DA transmit interface. 3.1 System description. 3.2 Reusable macromodels. 4 Summary.

CHAPTER 4 - THE ANALOG REUSABLE BLOCK: STRUCTURAL FACET. 1 Introduction. 1.1 Adopted sizing approach. 2 Design knowledge encapsulation. 2.1 Netlist-related elements . 2.1.1 Design variables. 2.1.2 Constraints. 2.2 Testbench setups. 2.2.1 Performance feature elements . 2.2.2 Peripheral setup elements. 2.2.3 Component model and process data elements. 2.2.4 Design variables, dependent variables, and constraints . 3 Practical aspects of structural view reuse. 4 Summary.

CHAPTER 5 - THE ANALOG REUSABLE BLOCK: LAYOUT FACET. 1 Introduction. 2 Layout retargeting . 2.1 Device mismatch. 2.2 Loading effects. 2.3 Coupling effects. 2.4 Reliability. 2.5 Area occupation. 3 Layout migration. 4 Analog layout strategies. 4.1 Optimization-driven approaches. 4.2 Knowledge-driven approaches. 5 Automated layout generation for design reuse. 6 Layout template: definition and properties. 7 Creating the layout template. 7.1 Device-level layout generation: primitives. 7.1.1 Reuse: migration issues. 7.1.2 Reuse: retargeting issues. 7.1.3 PDLP coding. 7.2 Device-level layout generation: blocks. 7.2.1 Reuse: migration issues. 7.2.2 Reuse: retargeting issues. 7.2.3 PDLB coding. 7.3 Layout template generation. 7.3.1 Reuse: migration issues. 7.3.2 Reuse: retargeting issues. 7.3.3 Layout template coding . 8 Practical implementation of layout-reusable analog blocks. 8.1 Layout languages. 8.2 Implementation examples. 9 Summary.

CHAPTER 6 - DESIGN EXAMPLES AND SILICON PROTOTYPE. 1 Introduction. 2 The demonstration vehicle . 2.1 Application area and rationale for architecture selection. 2.2 System specifications and specifications of the analog back-end. 2.3 Hierarchy of the analog back-end. 2.4 Analysis of the analog back-end. 2.4.1 The CT-LP filter. 2.4.2 The PGA. 3 Reusable blocks. 3.1 Reusable blocks: opamps. 3.2 Reusable blocks: analog back-end. 4 Design examples. 4.1 Design example (I): design retargeting and migration of the opamp. 4.1.1 Opamp retargeting in process A (0.35mm). 4.1.2 Opamp migration to process B (0.5mm). 4.2 Design example (II): GSM retargeting of the analog back-end. 4.3 Design example (III): multi-standard retargeting of the analog back-end. 4.4 Automation prototype. 5 Silicon prototype. 6 Costs and benefits. 7 Summary.

CHAPTER 7 - LAYOUT-AWARE CIRCUIT SIZING. 1 Introduction. 2 Geometrically constrained sizing. 2.1 Formulation of the problem. 2.2 Review of previous approaches. 2.3 An integrated approach. 2.4 Experimental results. 3 Parasitic-aware sizing. 3.1 Layout parasitics. 3.2 Extraction methods. 3.3 Extraction of parasitics in the design process. 3.4 Demonstration of the parasitic-aware design flow. 4 Summary.

APPENDIX A: ANALOG AND MIXED-SIGNAL LAYOUT RULES. 1 Device matching. 1.1 MOS transistors. 1.2 Passive resistors. 1.3 Passive capacitors. 2 Loading effects. 2.1 MOS transistors 3 Coupling effects. 3.1 Substrate coupling. 3.2 Coupling between routing wires. 4 Reliability. 4.1 MOS transistors. 4.2 Passive resistors. 4.3 Routing. 5 Area occupation. 5.1 MOS transistors. 5.2 Passive resistors. 5.3 Passive capacitors.

REFERENCES.