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Book Categories |
List of Figures | ||
List of Tables | ||
Preface | ||
1 | Introduction | 1 |
2 | Survey of Simulation and Macromodeling Techniques | 15 |
3 | A Nonlinear Macromodel | 93 |
4 | Reduction Techniques for Complex Gates | 125 |
5 | Accounting for RC-Interconnects | 171 |
6 | Transmission Gate Modeling | 191 |
7 | Conclusions | 199 |
A The Spice Level 2 Model | 205 | |
B Nonlinear Macromodel Output Response Derivations | 207 | |
C The Derivation of M = 0.5 Heuristic in Reduction Techniques | 213 | |
D Delay Errors for Various AOI Gates | 215 | |
References | 231 | |
Index | 261 |
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Add Digital Timing Macromodeling For Vlsi Design Verification, Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch, Digital Timing Macromodeling For Vlsi Design Verification to the inventory that you are selling on WonderClubX
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Add Digital Timing Macromodeling For Vlsi Design Verification, Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch, Digital Timing Macromodeling For Vlsi Design Verification to your collection on WonderClub |