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Book Categories |
| Foreword | ||
| Preface | ||
| Contributors | ||
| 0 | Giving Semantics to VHDL: An Introduction | 1 |
| 1 | A Functional Semantics for Delta-Delay VHDL Based on Focus | 9 |
| 2 | A Functional Semantics for Unit-Delay VHDL | 43 |
| 3 | An Operational Semantics for a Subset of VHDL | 71 |
| 4 | A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines | 107 |
| 5 | A Formal Model of VHDL Using Coloured Petri Nets | 140 |
| 6 | A Deterministic Finite-State Model for VHDL | 170 |
| 7 | A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL | 205 |
| References | 239 |
| Price | Condition | Delivery | Seller | Action |
| $191.04 | Digital |
| WonderClub |
Richard Sudborough
reviewed Formal Semantics for VHDL on January 10, 2014
Formal Semantics for VHDL
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Add Formal Semantics for VHDL, It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verificat, Formal Semantics for VHDL to the inventory that you are selling on WonderClubX
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Add Formal Semantics for VHDL, It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verificat, Formal Semantics for VHDL to your collection on WonderClub |
