Formal Equivalence Checking and Design Debugging Book

Formal Equivalence Checking and Design Debugging, Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes , Formal Equivalence Checking and Design Debugging

3 out of 5 stars based on 2 reviews

Formal Equivalence Checking and Design Debugging
Written by author Shi-Yu Huang
Published by Springer-Verlag New York, LLC, September 2007
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and descri

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Foreword
Preface
Ch. 1 Introduction 1
Ch. 2 Symbolic Verification 17
Ch. 3 Incremental Verification for Combinational Circuits 39
Ch. 4 Incremental Verification for Sequential Circuits 61
Ch. 5 AQUILA: A Local BDD-based Equivalence Verifier 91
Ch. 6 Algorithm for Verifying Retimed Circuits 111
Ch. 7 RTL-to-Gate Verification 123
Ch. 8 Introduction to Logic Debugging 139
Ch. 9 Error Tracer: Error Diagnosis by Fault Simulation 159
Ch. 10 Extension to Sequential Error Diagnosis 175
Ch. 11 Incremental Logic Rectification 189
Bibliography 211
Index 223

Title: Formal Equivalence Checking and Design Debugging

Manufacturer:

Steidl Publishing

Item Number: 9780792381846

Publication Date: September 2007

Number: 2

Product Description: Formal Equivalence Checking and Design Debugging

Universal Product Code (UPC): 9780792381846

WonderClub Stock Keeping Unit (WSKU): 9780792381846

Rating: 3/5 based on 2 Reviews

Image Location: https://wonderclub.com/images/covers/18/46/9780792381846.jpg

Category: Media >> Books

Weight: 0.200 kg (0.44 lbs)

Width: 9.210 cm (3.63 inches)

Heigh : 6.140 cm (2.42 inches)

Depth: 0.630 cm (0.25 inches)

Date Added: August 25, 2020, Added By: Ross

Date Last Edited: August 25, 2020, Edited By: Ross

Price	Condition	Delivery	Seller	Action
$181.44	Digital	Arrives between May 10 - Jun 9 Login to your account for a direct download. Some files are emailed from Dropbox. Continent $0.00 - World $0.00	WonderClub (9296 total ratings)

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Ernie Bautista

reviewed Formal Equivalence Checking and Design Debugging on July 31, 2013

Formal Equivalence Checking and Design Debugging

One of a very few mathematical books I could recommend to a non-mathematical person.

I think anyone with a visual sensitivity could page through this and enjoy the pictures.

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Formal Equivalence Checking and Design Debugging, Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes , Formal Equivalence Checking and Design Debugging

Add Formal Equivalence Checking and Design Debugging, Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes , Formal Equivalence Checking and Design Debugging to the inventory that you are selling on WonderClub

Add Formal Equivalence Checking and Design Debugging, Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes , Formal Equivalence Checking and Design Debugging to your collection on WonderClub

Formal Equivalence Checking and Design Debugging Book

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Steidl Publishing

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	Foreword
	Preface
Ch. 1	Introduction	1
Ch. 2	Symbolic Verification	17
Ch. 3	Incremental Verification for Combinational Circuits	39
Ch. 4	Incremental Verification for Sequential Circuits	61
Ch. 5	AQUILA: A Local BDD-based Equivalence Verifier	91
Ch. 6	Algorithm for Verifying Retimed Circuits	111
Ch. 7	RTL-to-Gate Verification	123
Ch. 8	Introduction to Logic Debugging	139
Ch. 9	Error Tracer: Error Diagnosis by Fault Simulation	159
Ch. 10	Extension to Sequential Error Diagnosis	175
Ch. 11	Incremental Logic Rectification	189
	Bibliography	211
	Index	223