2001 International Symposium on Semiconductor Manufacturing Book

	A Comparison of Unified vs. Segregated Automated Material Handling Systems for 300mm Fabs	3
	Agile Fab Concepts for Cost Effective and QTAT Mini Fab	7
	Cleanroom Design for Cu-CMP Processes	11
	Interoperable Communication Specification for AMHS	15
	Unified Tool Communication Specification for 300mm Automated Fab	19
	Managing, Measuring and Improving Equipment Capacity and Overall Equipment Efficiency (O.E.E.) Using iPlus	25
	TEKPAC (Technical Electronic Knowledge Personal Assistant Capsule)	29
	Optimization and Economic Analysis of Tool Portfolio Planning in Semiconductor Manufacturing	33
	The Economic Impact of Choosing Off-line, Inline or Insitu Metrology Deployment in Semiconductor Manufacturing	37
	B2B in TSMC Turnkey Services	41
	The Development of Security System and Visual Service Support Software for On-Line Diagnostics	45
	Wafer Level Tracking and Control to Full Mini-environment Line	51
	Universal Architecture to Improve Equipment Maintenance Work	55
	A New Manufacturing Control System Using Mahalanobis Distance for Maximising Productivity	59
	Using Real Time Dispatcher as a Decision-Making Support System to Resolve Overlapping Dispatching Problem in FAB Manufacturing	63
	Comprehensive Cost-Effective Photo Defect Monitoring Strategy	67
	Dynamic Simulator for WIP Analysis in Semiconductor Manufacturing	71
	Optimal Etch Time Control Design Using Neuro-Dynamic Programming	75
	Simple Tool of Analysis for Cycle Time Reduction	79
	Dynamical Control Method of AMHS for Multi-Production Lines	83
	Two Approaches to Determine Appropriated Fab Manufacturing Production Plan By Cycle-Time and Wip Energy	87
	Material Management System with the Function of Estimated Number Based on Production Control System	91
	Comprehensive Cycle Time	95
	An Automatic Monitor Management System for Effective 300mm Fab Operations	99
	Talking Shop - Linking Training to Factory Indicators	103
	Reconciling High-Speed Scheduling with Dispatching in Wafer Fabs	107
	Lithography-less Ion Implantation Technology for Agile Fab	113
	Novel Pulse Pressure CVD for Void Free STI Trench TEOS Fill	117
	Wafer Ambient Control for Agile FAB	121
	Improvement of CD Uniformity in 180nm LSI Manufacturing by Optimizing Illumination System	125
	Phi-Scatterometry for Integrated Linewidth Control in DRAM Manufacturing	129
	Full Profile Inter-Layer Dielectric CMP Analysis	133
	Towards a Complete Plasma Diagnostic System	137
	Spectroscopic CD Technology for Gate Process Control	141
	Multi-Wafer Rapid Isothermal Processing	145
	Plasma Charging Defect Inspection and Monitors in Poly-Buffered STI	149
	Development of a 2-Step Electroplating Process with a Long-Term Stability for Applying to Cu Metallization of 0.1[mu]m Generation Logic ULSIs	155
	Control of FSG/SiO[subscript 2] Interlayer Conditions to Prevent Al-wiring Delamination Caused by F Accumulation at Ti/SiO[subscript 2]	159
	Characterization of Metallic Impurities for the ULSI Fabrication Process	163
	Pseudo Epi, Materials Cost Reduction	167
	Data Mining and Fault Diagnosis Based on Wafer Acceptance Test Data and In-line Manufacturing Data	171
	Suppression of MOSFET Reverse Short Channel Effect by Channel Doping Through Gate Electrode	175
	Base Oxide Scaling Limit of Thermally-Enhanced Remote Plasma Nitridation (TE-RPN) Process for Ultra-Thin Gate Dielectric Formation	179
	Control of Edge Polishing Profile with Air Float Carrier	183
	Scaling Challenges for 0.13[mu]m Generation Shallow Trench Isolation	187
	Microeconomics of Accelerated Shrinks in Demand-Limited Markets	191
	Shallow Trench Isolation Scatterometry Metrology in a High Volume Fab	195
	Photo Resist Stripping Using Novel Sulfuric/Ozone Process	199
	Low k Material Optimization	203
	Multiple Objective APC Application for an Oxide CMP Process in a High Volume Production Environment	207
	Low Cost and High Reliability CMOS Technologies, by "Retro Process Sequence"	211
	Benchmarking 193nm Photoresists for Etch Resistance	215
	An Environmentally Friendly Photo Resist and Ashing Residue Remover for Cu/Low-k Devices	221
	Resource Conservation of Buffered HF in Semiconductor Manufacturing	225
	Reduction of PFC Emissions by Gas Circulation Cleaning in Plasma CVD	229
	Development of Photo-resist Stripping Process Using Ozone and Water Vapor	233
	Highly Sensitive Inspection System for Lithography-Related Faults in Agile Fab - Detecting Algorithm, Monitoring and Evaluation of Yield Impact	239
	A Plausible Model and Solutions for HSQ Volume Shrinkage of Aluminum Landing Pad	243
	New Method of Extraction of Systematic Failure Component	247
	Nanoscale Fault Isolation Technique by Conducting Atomic Force Microscopy	251
	Yield Improvement by Avoiding a Metal Chemical Reaction in the Metal Etching Post-Treatment	255
	Novel Strategies of FSG - CMP for Within-Wafer Uniformity Improvement and Wafer Edge Yield Enhancement Beyond 0.18 Micro Technologies	259
	Layout Manufacturability Analysis Using Rigorous 3-D Topography Simulation	263
	Yield Improvement Through Cycle Time and Process Fluctuation Analyses	267
	Acceleration of Yield Enhancement Activity by Utilizing Real-Time Fail Bitmap Analysis	271
	Characterization Algorithm of Failure Distribution for LSI Yield Improvement	275
	A Non-traditional Approach to Resolving Multi-layer Process-induced Metal Voiding	279
	Methodology for Yield Analysis based on Targeted Defect Impact Studies	283
	Silicide Related Yield Enhancement in a Deep Submicrometer CMOS	287
	Study of High Density Plasma Etch for Borderless Contact to Solve Bottom Anti-Reflective Coating Defect for Beyond 0.18[mu]m VLSI Technology	291