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Book Categories |
Message from the Chairs | ||
Conference Committee | ||
TTTC Information | 180 | |
Embedded Memory Test and Repair | ||
Defect-Oriented Analysis of Memory BIST Tests | 7 | |
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques | 12 | |
A Scan-Bist Environment for Testing Embedded Memories | 17 | |
Soft Error Protection for Embedded Memories | ||
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories | 27 | |
High Speed 15 ns 4 Mbits SRAM for Space Application | 32 | |
The YATE Fail-Safe Interface: The User's Point of View | 39 | |
Fault Tolerant Insertion and Verification: A Case Study | 44 | |
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems | 49 | |
A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios | 57 | |
A March-Based Fault Location Algorithm for Static Random Access Memories | 62 | |
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories | 68 | |
Challenges and Opportunities Created by the SoC Shockwave | ||
Design and Test of a 9-Port SRAM for a 100 Gb/s STS-1 Switch | 83 | |
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process | ||
Adder Merged DRAM Architecture | 88 | |
March SS: A Test for All Static Simple RAM Faults | 95 | |
Random Testing of Multi-Port Static Random Access Memories | 101 | |
A Fault Modeling Technique to Test Memory BIST Algorithms | 109 | |
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM | 117 | |
An Investigation into Crosstalk Noise in DRAM Structures | 123 | |
SoC's Trends and Challenges going to 0.10 [mu]m | ||
An Automated Design Methodology for EEPROM Cell (ADE) | 137 | |
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology | 143 | |
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories | 149 | |
Validated 90 nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) | ||
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI | 163 | |
Decreasing EEPROM Programming Bias with Negative Voltage, Reliability Impact | 168 | |
Panel on Advanced Embedded Memory Technologies | 177 | |
Author Index | 179 |
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