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Preface | xi | |
Acknowledgments | xvii | |
1 | Introduction | 1 |
1.1 | History of the Profession | 1 |
1.2 | What Is Layout Design? | 2 |
1.3 | IC Design Flow | 4 |
2 | Schematic Fundamentals | 7 |
2.1 | The MOS Transistor: The Basic Circuit Structure | 7 |
2.2 | Logic Gates | 10 |
2.3 | Transmission Gates | 16 |
2.4 | Understanding the Schematic Connectivity | 17 |
2.5 | Review of Fundamental Electrical Laws | 18 |
3 | Layout Design | 22 |
3.1 | Introduction to CMOS VLSI Manufacturing Process | 22 |
3.2 | Layers and Connectivity | 23 |
3.3 | Introduction to Transistor Layout | 28 |
3.4 | Process Design Rules | 35 |
3.5 | Vertical Connection Diagram | 41 |
3.6 | A General Procedure to Follow | 42 |
3.7 | Preparing to Start | 43 |
3.8 | General Guidelines | 50 |
3.9 | Implementing the Design | 59 |
3.10 | Verification | 63 |
3.11 | Final Steps | 65 |
4 | Layout Design Flows | 68 |
4.1 | What Is a Flow? | 68 |
4.2 | Microprocessor Design Flow | 71 |
4.3 | ASSPs | 73 |
4.4 | Memories | 77 |
4.5 | System on a Chip, or SOC | 78 |
4.6 | CAD Tools as Part of a Flow | 79 |
5 | Advanced Techniques for Specialized Building-Block Layout Design | 91 |
5.1 | Standard Cell Libraries | 91 |
5.2 | Special Logic Cells | 107 |
5.3 | Pad Cells | 114 |
5.4 | Memory Design Leaf Cells | 123 |
5.5 | Laser Fuse Cells | 129 |
5.6 | Chip Finishing Cells | 132 |
6 | Advanced Techniques for Building-Block Interconnect Layout Design | 137 |
6.1 | Power Grid | 138 |
6.2 | Clock Signals | 141 |
6.3 | Interconnect Routing | 143 |
7 | Layout Design Techniques to Address Electrical Characteristics | 154 |
7.1 | Resistance | 154 |
7.2 | Capacitance | 159 |
7.3 | Symmetry | 169 |
7.4 | Special Electrical Requirements | 175 |
8 | Layout Considerations Due to Process Constraints | 183 |
8.1 | Wide Metal Slits | 183 |
8.2 | Large Metal via Implementations | 186 |
8.3 | Step Coverage Rules | 187 |
8.4 | Multiple Rule Sets | 189 |
8.5 | Antenna Rules | 191 |
8.6 | Special Design Rules | 192 |
8.7 | Latch-Up | 194 |
9 | Layout Design Techniques in an Uncertain Environment | 201 |
9.1 | Layout of Circuits Designed for Change | 201 |
9.2 | Planning for Unknown Changes | 207 |
9.3 | Engineering Change Orders | 211 |
9.4 | Guidelines for Proper Layout | 213 |
10 | Computer-Aided Design (CAD) Tools for Layout | 216 |
10.1 | Introduction | 216 |
10.2 | Planning Tools | 219 |
10.3 | Layout Generation Tools | 224 |
10.4 | Support Tools | 236 |
Appendices | 245 | |
Index | 257 |
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Add CMOS IC Layout: Concepts, Methodologies, and Tools, This book includes basic methodologies, review of basic electrical rules and how they apply, design rules, IC planning, detailed checklists for design review, specific layout design flows, specialized block design, interconnect design, and also additional, CMOS IC Layout: Concepts, Methodologies, and Tools to the inventory that you are selling on WonderClubX
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Add CMOS IC Layout: Concepts, Methodologies, and Tools, This book includes basic methodologies, review of basic electrical rules and how they apply, design rules, IC planning, detailed checklists for design review, specific layout design flows, specialized block design, interconnect design, and also additional, CMOS IC Layout: Concepts, Methodologies, and Tools to your collection on WonderClub |