VLSI '93: Proceedings of the IFIP TC10 - WG10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September 1993 Book

	The single chip system era	3
	Post-placement technology mapping	15
	Optimal layout recycling based on graph theoretic linear programming approach	25
	A family of module generators for the layout synthesis of I/O buffers	35
	A 45[degree] compaction algorithm handling overconstraints	45
	Personal Communicators: A better way to stay in touch	57
	Design of a GaAs redundant divider	63
	An ASIC array architecture for the DITPOS algorithm	73
	Performance of object caching for object-oriented systems	83
	A VLSI circuit for on-line polynomial computing: Application to exponential, trigonometric and hyperbolic functions	93
	Self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design	103
	Partitioning and hierarchical description of self-testable designs	113
	Test of single fault tolerant controllers in VLSI circuits	123
	A C-testable parallel multiplier using differential cascode voltage switch (DCVS) logic	133
	Opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensors	145
	Single board image processing unit for vehicle guidance	151
	Implementation of the volume rendering algorithm using a low-power design-style	161
	Design of a dedicated neural network on silicon: application to optical character recognition	169
	ARM6: Processor design for high performance at low power	181
	A new method for retiming multi-functional processing units	191
	A transformational approach to asynchronous high-level synthesis	201
	A micropipelined ARM	211
	A high performance RISC microprocessor	221
	Probabilistic power consumption estimation in digital circuits	231
	Solving the partial differential equations of transmission lines with wave digital filters	241
	Parallel harmonic balance	251
	Estimating lower hardware bounds in high-level synthesis	261
	Ultra high speed CMOS design	273
	The implementation of a MCM associative string processor	283
	Superconductive interconnections in multi-chip modules	291
	A multilayer channel router based on optimal multilayer net assignment	301
	The chaos router chip: design and implementation of an adaptive router	311
	A new performance-driven global routing algorithm for gate array	321
	Circuit simulation for large interconnected IC networks	333
	Bondgraph execution as a new algorithm for circuit simulation	343
	Adaptive checkpoint intervals in an optimistically synchronised parallel digital system simulator	353
	Author Index	363