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A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architecture Book

A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architecture
A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architecture, , A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architecture has a rating of 3 stars
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  • A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architecture
  • Written by author Ian N. Dunn
  • Published by Springer-Verlag New York, LLC, September 2007
  • Dunn (Mercury Computer Systems) and Meyer (computer engineering, John Hopkins University) present a parallel algorithm synthesis procedure that introduces parameters to control the partitioning and scheduling of computation and communication with the goal
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Book Categories

Authors

List of Figures
List of Tables
Acknowledgments
1Introduction
1Notation and Conventions
2Chapter Organization
2Parallel Computing
1Architectures
2Programming Models
3Performance Metrics
3Parallel Algorithm Synthesis Procedure
1Architectural Model for Algorithm Synthesis
2Synthesis Procedure
3Related Work
4Review of Matrix Factorization
1Givens-based Solution Procedures
2Householder-based Solution Procedures
5Case Study 1: Parallel Fast Givens QR
1Parallel Fast Givens Algorithm
2Communication Procedures
3Related Work
4Experimental Results
6Case Study 2: Parallel Compact WY QR
1Parallel Compact WY Algorithm
2Related Work
3Experimental Results
7Case Study 3: Parallel Bidiagonalization
1Parallel Matrix Bidiagonalization Algorithm
2Related Work
3Experimental Results
8Conclusion
References
Index


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