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2003 Southwest Symposium on Mixed-Signal Design Book

2003 Southwest Symposium on Mixed-Signal Design
2003 Southwest Symposium on Mixed-Signal Design, , 2003 Southwest Symposium on Mixed-Signal Design has a rating of 4 stars
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2003 Southwest Symposium on Mixed-Signal Design, , 2003 Southwest Symposium on Mixed-Signal Design
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  • 2003 Southwest Symposium on Mixed-Signal Design
  • Written by author Circuits and Systems Society Staff IEEE
  • Published by I.E.E.E.Press, 2003/06/30
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Book Categories

Authors

System-on-chip or system-on-package : can we make an accurate decision on system implementation in an early design phase? 1
Automatic synthesis using genetic programming of both the topology and sizing for five post-2000 patented analog and mixed analog-digital circuits 5
Software tool for design and simulation of data converters 11
Considerations for an analog and mixed-signal computer aided design tool 15
Addressing a high-speed D/A converter design for mixed-mode VLSI systems 21
Reconfigurable ADC for 3-G UTRA-TDD mobile receiver 27
Method of segmenting digital-to-analog converters 32
A low power 25MS/S 12-bit pipelined analog to digital converter for wireless applications 38
Design and implementation of electrical-supply-free VLSI circuits 43
Low power and noise tolerant 20 GB/S CMOS TIA for short-distance optical interconnect 49
VLSI interconnect modeling at multi-GHZ frequencies incorporating inductance 54
Low impedance line structure component (LILC) for power distribution system in the high-performance digital circuit 60
Flow for phase locked loop mixed signal simulation and characterization using behavioral modeling 66
A study of nonlinearities for a frequency-locked loop principle 71
Phase interpolator using delay locked loop 76
Loop filter design considerations for clock and data recovery circuit 81
Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications 87
A 4-KB 667-MHZ CMOS SRAM using dynamic threshold voltage wordline transistors 90
Experimental characterization of a self-calibrating delay-locked delay-line 94
Design of a new linear OTA with a mobility compensation technique 99
Novel constant transconductance references and the comparisons with the traditional approach 104
A low voltage CMOS current source with temperature compensation 108
A simple yet accurate analytical method for reducing CMOS gates to equivalent interters 112
Power and delay estimation of CMOS inverters using fully analytical approach 116
Thermal noise from switches in a switched-capacitor gain stage 121
RF performance degradation due to coupling of digital switching noise in lightly doped substrates 127
Power-line noise coupling estimation methodology for architectural exploration of mixed-signal systems 133
Large-signal characterization and modeling of a silicon bipolar techonology for high-efficiency power applications up to c-band 138
A comparative analysis of monolithic spiral inductors in silicon bipolar technology 144
Influence of back-end architectures on the performance of RF CMOS VCOS 150
A long-channel model for the asymmetric double-gate MOSFET valid in all regions of operation 156
Modeling of switched current memory cell with VHDL-AMS for mixed system design 162
Macromodeling with spice for the voltage breakdown behavor in bipolar junction and field-effect transistors 166
Modeling and time domain simulation of VCSEL using VHDL-AMS 170
A programmable interface circuit for inductive position sensors 175
A floating gate common mode feedback circuit for low noise amplifiers 180
Switched-current 3-bit CMOS wideband random signal generator 186
Offset removal using floating-gate circuits for mixed-signal systems 190
A mixed-signal built-in self-test approach for analog circuits 196
Defining a bist-oriented signature for mixed-signal devices 202
A high-speed dynamic current sensor for IDD test based on the flipped voltage follower 208
Fault injection emulation for field programmable analog arrays 212
A wireles FM multi-channel microsystem for biomedical neural recording applications 217
A fully digital frequency shift keying demodulator chip for wireless biomedical implants 223
64-channel ultrasound transducer amplifier 228
Candidate generation for 45 degree routing for mixed-signal layout 233
A novel timing-driven placement using genetic algorithm 237
Cluster growth revisited : fast, mixed-signal placement of blocks and gates 243
A compact phase interpolator for 3.125G serdes application 249
A 750MW class G ADSL line driver with offset-controlled amplifier hand-over 253
Stable boundaries of a third-order sigma-delta modulator 259
An enhanced dynamic range low power delta-digma modulator for portable voice band applications 263


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