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2003 33rd European Conference Solid States Circuits Book

2003 33rd European Conference Solid States Circuits
2003 33rd European Conference Solid States Circuits, , 2003 33rd European Conference Solid States Circuits has a rating of 3 stars
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2003 33rd European Conference Solid States Circuits, , 2003 33rd European Conference Solid States Circuits
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  • 2003 33rd European Conference Solid States Circuits
  • Written by author IEEE Solid-State Circuits Society Staff
  • Published by I E E E, 1/1/2003
Buy Digital  USD$162.49

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Complex signal processing is not - complex 3
Taking a system approach to energy management 15
RF - trends in mobile communication 21
Transistor operation and circuit performance in organic electronics 29
Emerging non-volatile memory technologies 37
IP related activities in Toshiba and Japanese SoC industries 45
A scaleable instruction buffer for a configurable DSP core 49
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals 53
An area-efficient standard-cell floating-point unit design for a processing-in-memory system 57
A 1000FPS@128x128 vision processor with 8-bit digitized I/O 61
An analog image processing LSI employing scanning line-parallel processing 65
Micropower mixed-signal acoustic localizer 69
A 50GHz direct injection locked oscillator topology as low power frequency divider in 0.13[mu]m CMOS 73
A 15GHz 256/257 dual-modulus prescaler in 120nm CMOS 77
A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18[mu]m CMOS 81
A digital quadrature modulator with on-chip D/A converter 85
A 12b 320MSample/s current-steering CMOS D/A converter in 0.44mm[superscript 2] 89
Single-side-band digital-to-analog converters for Nyquist signal generation 93
A [Sigma]-[Delta] fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications 97
A compact, low-power low-jitter digital PLL 101
A low voltage, 10-2550MHz, 015[mu] CMOS, process and divider modulus independent PLL using zero-VT MOSFETs 105
A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delay 109
A 1-V 5.2-GHz 27.5-mW fully-integrated CMOS WLAN synthesizer 113
A CMOS photodiode array with in-pixel data acquisition system 117
CMOS x-ray image sensor with pixel level A/D conversion 121
A smart image sensor with high-speed feeble ID-beacon detection for augmented reality system 125
A CMOS focal-plane rotation sensor with retinal processing circuit 129
A readout circuit for QWIP infrared detector arrays using current mirroring integration 133
Linearization of monolithic LNAs using low-frequency low-impedance input termination 137
A 1.8-V wide-band CMOS LNA for multiband multistandard front-end-receiver 141
Design of high gain fully-integrated distributed amplifiers in 0.35[mu]m CMOS 145
17GHz and 24GHz LNA designs based on extended-s-parameter with microstrip-on-die in 0.18[mu]m logic CMOS technology 149
Inductor-less, 10Gb/s limiter with 10mV sensitivity and offset/temperature compensation in baseline CMOS18 153
A fully-integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers 157
A 16-bit 60[mu]W multi-bit [Sigma][Delta] modulator for portable ECG applications 161
A micro power continuous-time [Sigma][Delta] modulator 165
A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technology 169
A low-power entropy-coding analog/digital converter with integrated data compression 173
Energy minimization method for optimal energy-delay extraction 177
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies 181
High performance pipelining method for static circuits using heterogeneous pipelining elements 185
A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design 189
An 8-channel, 12-bit, 20 MHz fully differential tester IC for analog and mixed-signal circuits 193
A serial 10 gigabit ethernet transceiver on digital 0.13[mu]m CMOS 197
A DSP-based digital IF AM/FM car-radio receiver
Custom silicon implementation of a delayless acoustic echo canceller algorithm 205
A novel universal battery charger for NiCd, NiMH, Li-ion and Li-polymer
A contactless smartcard designed with asynchronous circuit technique 213
A quad-band low power single chip direct conversion CMOS transceiver with [Sigma][Delta]-modulation loop for GSM
A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18[mu]m CMOS RF transceiver for 802.11a/b/g wireless LAN
A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b
A highly integrated, dual-band, multi-mode wireless LAN transceiver 229
A 15 MHz bandwidth Sigma-Delta ADC with 11 bits of resolution in 0.13[mu]m CMOS 233
A 400-MHz 6-bit ADC with a partial analog equalizer for coaxial cable channels 237
A 1.8V 100mW 12bits 80Msample/s two-step ADC in 0.18[mu] CMOS 241
A 10-bit, 3 mW continuous-time Sigma-Delta ADC for UMTS in a 0.12[mu]m CMOS process 245
A continuous-time Sigma-Delta modulator with switched capacitor controlled current mode feedback 249
Modeling impact of digital substrate noise on embedded regenerative comparators 253
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate 257
Aggressor aware repeater circuits for improving on-chip bus performance and robustness 261
Clock net optimization using active shielding 265
Passive integration and RF MEMS : a toolkit for adaptive LC circuits 269
Single chip, low supply voltage piezoelectric transformer controller 273
24Gb/s laser/modulator drive IC using 0.2[mu]m gate length PHEMTs 277
A CMOS 10Gb/s SONET transceiver 281
A 10 Gb/s CMOS limiting amplifier for optical links 285
10Gb/s single-ended laser driver in 0.35[mu]m SiGe BiCMOS technology 289
A CMOS single-ended OTA with high CMRR 293
A 0.8-V, 8[mu]W, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load 297
A 1.8-V 73-dB dynamic-range CMOS variable gain amplifier 301
Optimization of device dimensions for high-performance low-power architecture blocks 305
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology 309
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies 313
A gate leakage reduction strategy for future CMOS circuits 317
Power - performance optimal 64-bit carry-lookahead adders 321
A CMOS receiver for a pulsed time-of-flight laser rangefinder 325
A micro-hotplate-based monolithic CMOS thermal analysis system 329
A 4x65 pixel CMOS image sensor for 3D measurement applications 333
DNA electrical detection based on inductor resonance frequency in standard CMOS technology 337
A Low-noise 1.8Gbps bipolar OEIC 341
A robust 43 GHz VCO in standard CMOS for OC-768 SONET applications 345
A 19-23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology 349
Fully-integrated 10 GHz CMOS VCO for multi-band WLAN applications 353
A 31 GHz CML ring VCO with 5.4ps delay in a 0.12[mu]m SOI CMOS technology 357


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