2001 6th International Workshop on Statistical Methodology for VLSI Design and Fabrication Book

	"Taguchi Methods in LSI fabrication process"
	"Robust design for VLSI process and device"
	"Device optimization using response surface methodology with orthogonal arrays"
	"Robust design of 0.18um ASIC MOSFETs suing Taguchi method with TCAD"
	"Wafer yield prediction by the Mahalanobis-Taguchi system"
	"Accurate prediction of deep submicron CMOS device characteristics using modeling techniques"
	"Effective defect management strategies for emerging fab needs"
	"Scaling variance, invariance and prediction of design rule: From 0.25-[mu]m to 0.10-[mu]m nodes in the era of foundry manufacturing"
	"A new extraction method of device parameters for mass production E-T data analysis"
	"Impact of nMOS/pMOS gate length correlation on the accuracy of statistical modeling"
	"Timing analysis taking into account interconnect process variations"
	"A Statistical design methodology of a 0.12-[mu]m CMOS device for MPU applications"
	"DC integration level analysis of low-Vdd CMOS circuit using worst-case noise margin map"
	"Impact analysis of process variability on digital circuits with performance limited yield"
	"Variation issues in on-chip optical clock distribution"