Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Book

	A power-efficient and scalable load-store queue design	1
	Power consumption reduction using dynamic control of micro processor performance	10
	Low power techniques applied to a 80C51 microcontroller for high temperature applications	19
	Dynamic instruction cascading on GALS microprocessors	30
	Power reduction of superscalar processor functional units by resizing adder-width	40
	A retargetable environment for power-aware code evaluation : an approach based on coloured petri net	49
	Designing low-power embedded software for mass-produced microprocessor by using a loop table in on-chip memory	59
	Energy characterization of garbage collectors for dynamic applications on embedded systems	69
	Optimizing the configuration of dynamic voltage scaling points in real-time applications	79
	Systematic preprocessing of data dependent constructs for embedded systems	89
	Temperature aware datapath scheduling	99
	Memory hierarchy energy cost of a direct filtering implementation of the wavelet transform	107
	Improving the memory bandwidth utilization using loop transformations	117
	Power-aware scheduling for hard real-time embedded systems using voltage-scaling enabled architectures	127
	Design of digital filters for low power applications using integer quadratic programming	137
	A high level constant coefficient multiplier power model for power estimation on high levels of abstraction	146
	An energy-tree based routing algorithm in wireless ad-hoc network environments	156
	Energy-aware system-on-chip for 5 GHz wireless LANs	166
	Low-power VLSI architectures for OFDM transmitters based on PAPR reduction	177
	An activity monitor for power/performance tuning of CMOS digital circuits	187
	Power management for low-power battery operated portable systems using current-mode techniques	197
	Power consumption in reversible logic addressed by a ramp voltage	207
	Leakage and dynamic glitch power minimization using integer linear programming for V[subscript th] assignment and path balancing	217
	Back annotation in high speed asynchronous design	227
	Optimization of reliability and power consumption in systems on a chip	237
	Performance gains from partitioning embedded applications in processor-FPGA SoCs	247
	A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design	257
	Power supply selective mapping for accurate timing analysis	267
	Switching sensitive driver circuit to combat dynamic delay in on-chip buses	277
	PSK signalling on NoC buses	286
	Exploiting cross-channel correlation for energy-efficient LCD bus encoding	297
	Closed-form bounds for interconnect-aware minimum-delay gate sizing	308
	Efficient simulation of power/ground networks with package and vias	318
	Output resistance scaling model for deep-submicron CMOS buffers for timing performance optimisation	329
	Application of internode model to global power consumption estimation in SCMOS gates	337
	Compact static power model of complex CMOS gates	348
	Energy consumption in RC tree circuits with exponential inputs : an analytical model	355
	Statistical critical path analysis considering correlations	364
	A CAD platform for sensor interfaces in low-power applications	374
	An integrated environment for embedded hard real-time systems scheduling with timing and energy constraints	382
	Efficient post-layout power-delay curve generation	393
	Power - performance optimization for custom digital circuits	404
	Switching-activity directed clustering algorithm for low net-power implementation of FPGAs	415
	Logic-level fast current simulation for digital CMOS circuits	425
	Design of variable input delay gates for low dynamic power circuits	436
	Two-phase clocking and a new latch design for low-power portable applications	446
	Power dissipation reduction during synthesis of two-level logic based on probability of input vectors changes	456
	Energy-efficient value-based selective refresh for embedded DRAMs	466
	Design and implementation of a memory generator for low-energy application-specific block-enabled SRAMs	477
	Static noise margin analysis of sub-threshold SRAM cells in deep sub-micron technology	488
	An adaptive technique for reducing leakage and dynamic power in register files and reorder buffers	498
	Parameter variation effects on timing characteristics of high performance clocked registers	508
	Low-power aspects of nonlinear signal processing	518
	Reducing energy consumption of computer display by camera-based user monitoring	528
	Controlling peak power consumption during scan testing : power-aware DfT and test set perspectives	540
	A design methodology for secured ICs using dynamic current mode logic	550
	Power consumption characterisation of the Texas instruments TMS320VC5510 DSP	561
	A method to design compact DUAL-RAIL asynchronous primitives	571
	Enhanced GALS techniques for datapath applications	581
	Optimizing SHA-1 hash function for high throughput with a partial unrolling study	591
	Area-aware pipeline gating for embedded processors	601
	Fast low-power 64-bit modular hybrid adder	609
	Speed indicators for circuit optimization	618
	Synthesis of hybrid CBL/CMOS cell using multiobjective evolutionary algorithms	629
	Power-clock gating in adiabatic logic circuits	638
	The design of an asynchronous carry-lookahead adder based on data characteristics	647
	Efficient clock distribution scheme for VLSI RNS-enabled controllers	657
	Power dissipation impact of the technology mapping synthesis on look-up table architectures	666
	The optimal wire order for low power CMOS	674
	Effect of post-oxidation annealing on the electrical properties of anodic oxidized films in pure water	684
	Temperature dependency in UDSM process	693
	Circuit design techniques for on-chip power supply noise monitoring system	704
	A novel approach to the design of a linearized widely tunable very low power and low noise differential transconductor	714
	A new model for timing jitter caused by device noise in current-mode logic frequency dividers	724
	Digital hearing aids : challenges and solutions for ultra low power	733
	Tutorial hearing aid algorithms	734
	Optimization of digital audio processing algorithms suitable for hearing aids	735
	Optimization of modules for digital audio processing	737
	Traveling the wild frontier of ultra low-power design	747
	DLV (deep low voltage) : circuits and devices	748
	Wireless sensor networks : a new life paradigm	749
	Cryptography : circuits and systems approach	750