Digital System Design Using Vhdl Book

Preface ..... xv

Chapter 1: VHDL Basics ..... 1
1.1 VHDL Historical Background ..... 1
1.2 Pseudo Concurrent Environment ..... 3
1.3 Entity Design Unit ..... 4
1.4 Architecture Design Unit ..... 7
1.5 Architecture with Multiple Concurrent Constructs ..... 9
1.6 VHDL Objects and Signals ..... 10
1.7 Simulation Cycles and Delta Cycles ..... 13
Exercises ..... 15

Chapter 2: Sequential Constructs and Description ..... 16
2.1 Lexical Elements and Literals ..... 16
2.2 Data Types ..... 17

a. Enumeration Type ..... 18
b. Numerical Type ..... 18
c. Physical Type ..... 18
d. Composite Type ..... 19
e. Record Type ..... 19

2.3 Predefined Operators ..... 21
2.4 Behavior Model and Process ..... 24
2.5 Conditional Control ..... 24
2.6 Loop, Exit, and Next Statements ..... 26
2.7 The Wait Statement ..... 29
2.8 Access Type, File Type, Declaration, and Textio Read ..... 30
2.9 Sequential and Concurrent Assertions ..... 32
2.10 Sequential Algorithm in a Process and TEXTIO ..... 32
Write
Exercises ..... 35
Problems ..... 37

Chapter 3: Concurrent Constructs and Description ..... 39
3.1 Concurrent Statements in Architecture ..... 39
3.2 Conditional and Selected Signal Assignment Statements ..... 39
3.3 Transport Delay, Inertial Delay, and Event Queue ..... 41

(a) Transportability ..... 41
(b) Inertial delay ..... 43
(c) Event queue ..... 45

3.4 Structural Description, Component Declaration, Instantiation, and Configuration Specification Statement ..... 45
3.5 Structure Model of a Full-adder ..... 49
3.6 Simple Combinational Circuits,Decoders, and Multiplexers ..... 52
3.7 Block, Guarded Block, Structure of a Full Adder, and Gated D_latch ..... 56
3.8 Minimum Delta Cycle Delay in Signal Assignment Exercises ..... 60
Problems ..... 60

Chapter 4: Advanced Features and Modeling ..... 63
4.1 Predefined Attributes ..... 63
4.2 Subprogram, Functions, and Procedures ..... 64

(a) Functions ..... 65
(b) Procedures ..... 65

4.3 Package Design Entity ..... 66
4.4 4-bit Comparator Behavior Model ..... 69
4.5 Edge Triggered Registers ..... 72
4.6 Shift Registers and Counters ..... 79
4.7 Library Use Statement, and Design Unit Visibility ..... 83
4.8 VHDL as a Stimulus Language and Test Bench ..... 84
4.9 User Defined Logic Values and Proposed Standard Logic Values ..... 87
4.10 Timing Modeling and Accuracy ..... 90

(a) Functional simulation without delay ..... 91
(b) Fixed delay approach ..... 91
(c) Rise/fall delay approach ..... 92
(d) Full delay approach ..... 93
(e) Timing error check ..... 94

4.11 Resolution Function and Multiple Drivers ..... 97
Exercises ..... 100
Problems ..... 101

Chapter 5: Top-Down Design Methodology for a Finite Impulse Response (FIR) Filter ..... 104
5.1 Introduction ..... 104
5.2 Test_bench of an FIR Filter ..... 104
5.3 Behavior Model of an FIR Filter ..... 107
5.4 Data Flow Model of an FIR Filter ..... 109
5.5 "Full Pipe" Structural Model of an FIR Filter ..... 111
5.6 "Half Pipe" Structural model of an FIR Filter ..... 117
5.7 "Clever" Structural model of an FIR Filter ..... 119
5.8 Gate Level Design Using Field Programmable Gate Array (FPGA) ..... 120
5.9 Top-Down Design Methodology ..... 126
Exercises ..... 127

Chapter 6: Behavior and Data Flow Modeling of a Simple Computer ..... 128
6.1 System Package ..... 128

(a) System Package Declaration ..... 128
(b) System Package Body ..... 129

6.2 A Simple 4-bit Computer ..... 133
6.3 Behavior Description of the Simple Computer ..... 136
6.4 A Data Flow Description ..... 141

(a) Program Counter (PC) Model ..... 142
(b) Accumulator (ACC) Model ..... 143
(c) B Register (B_REG) Model ..... 144
(d) Instruction Register (IR) Model ..... 145
(e) Temporary Address Register (TAR) Model ..... 145
(f) Arithmetic Logic Unit (ALU) Model ..... 146
(g) Random Access Memory (RAM) Model ..... 147
(h) Controller Model ..... 148

6.5 Test_bench of the Simple Computer ..... 157
Exercises ..... 163

Chapter 7: Design of Fast Fourier Transform (FFT) System ..... 164
7.1 Fast Fourier Transform and Butterfly Operation ..... 164
7.2 FFT Behavior Model and an 8-point test vector ..... 167
7.3 FFT System Component ..... 170

(a) Butterfly (Fly) ..... 172
(b) Dual RAM (DRAM) ..... 173
(c) Read Only Memory (ROM) ..... 175
(d) Multiplexer (CMUX) ..... 175

7.4 Sequence Generator and FFT Simulation ..... 176
7.5 Pipe-line Implementation of an FFT Butterfly ..... 185
7.6 Single FPU Butterfly and Fly Control ..... 190
7.7 Top Down Design Methodology Using VHDL ..... 196
Exercises ..... 197
Problems ..... 198

Chapter 8: Modeling of Communication Protocol SCSI ..... 199
8.1 SCSI Bus Signals ..... 199
8.2 Open Collector Bus Driver ..... 202
8.3 Single Initiator-Single Target, No Arbitration ..... 204

(a) Bus Free Phase ..... 205
(b) Selection Phase No Arbitration ..... 205
(c) Data Transfer Phase ..... 205

8.4 A Simple Functional Model For Data Out Handshake ..... 209
8.5 A Model With More Accurate Selection Phase ..... 212
8.6 Initiator with Arbitration ..... 216

(1) Arbitration Phase ..... 216
(2) Selection Phase with Arbitration ..... 218

8.7 A Model of One Initiator with Priority ..... 220
8.8 A Model of Two Initiators With Priority ..... 225
Exercises ..... 231

Chapter 9: Structural Modeling of Erasable Programmable Logic Devices (EPLD) ..... 232
9.1 What is an EPLD ..... 232
9.2 Timing Model Primitives for EPROM ..... 235
9.3 Structural Description of the EP310 ..... 236

(a) P_term Entity ..... 237
(b) AND_OR Array and Concurrent Generate Statement ..... 241
(c) D_register Entity ..... 242
(d) IO_control Entity ..... 244

9.4 The EP310 Entity and Test_bench ..... 246
9.5 From a Counter to a Design JEDEC File ..... 251
Exercises ..... 253

Appendix A. VHDL Reserved Wrods ..... 254

Appendix B. Package STANDARD ..... 255

Appendix C. Package TEXTIO ..... 257

Appendix D. Suggested Reading ..... 260

Appendix E. VHDL 1992 Restandardization ..... 262

Index ..... 264