Advanced Asic Chip Synthesis Using Synopsys. Design Compiler. Physical Compiler. And Primetime. Book

	Foreword	xv
	Preface	xvii
	Acknowledgments	xxiii
	About The Author	xxv
Chapter 1	Asic Design Methodology	1
1.1	Traditional Design Flow	2
1.1.1	Specification and RTL Coding	4
1.1.2	Dynamic Simulation	5
1.1.3	Constraints, Synthesis and Scan Insertion	6
1.1.4	Formal Verification	8
1.1.5	Static Timing Analysis using PrimeTime	10
1.1.6	Placement, Routing and Verification	11
1.1.7	Engineering Change Order	12
1.2	Physical Compiler Flow	13
1.2.1	Physical Synthesis	16
1.3	Chapter Summary	17
Chapter 2	Tutorial	19
2.1	Example Design	20
2.2	Initial Setup	21
2.3	Traditional Flow	22
2.3.1	Pre-Layout Steps	22
2.3.2	Post-Layout Steps	36
2.4	Physical Compiler Flow	42
2.5	Chapter Summary	42
Chapter 3	Basic Concepts	45
3.1	Synopsys Products	45
3.2	Synthesis Environment	48
3.2.1	Startup Files	48
3.2.2	System Library Variables	49
3.3	Objects, Variables and Attributes	51
3.3.1	Design Objects	51
3.3.2	Variables	52
3.3.3	Attributes	53
3.4	Finding Design Objects	54
3.5	Synopsys Formats	55
3.6	Data Organization	55
3.7	Design Entry	56
3.8	Compiler Directives	57
3.8.1	HDL Compiler Directives	58
3.8.2	VHDL Compiler Directives	60
3.9	Chapter Summary	61
Chapter 4	Synopsys Technology Library	63
4.1	Technology Libraries	64
4.1.1	Logic Library	64
4.1.2	Physical Library	64
4.2	Logic Library Basics	65
4.2.1	Library Group	65
4.2.2	Library Level Attributes	66
4.2.3	Environment Description	66
4.2.4	Cell Description	71
4.3	Delay Calculation	74
4.3.1	Delay Model	74
4.3.2	Delay Calculation Problems	76
4.4	What is a Good Library?	77
4.5	Chapter Summary	79
Chapter 5	Partitioning and Coding Styles	81
5.1	Partitioning for Synthesis	82
5.2	What is RTL?	84
5.2.1	Software versus Hardware	84
5.3	General Guidelines	85
5.3.1	Technology Independence	85
5.3.2	Clock Related Logic	85
5.3.3	No Glue Logic at the Top	86
5.3.4	Module Name Same as File Name	86
5.3.5	Pads Separate from Core Logic	87
5.3.6	Minimize Unnecessary Hierarchy	87
5.3.7	Register All Outputs	87
5.3.8	Guidelines for FSM Synthesis	87
5.4	Logic Inference	88
5.4.1	Incomplete Sensitivity Lists	88
5.4.2	Memory Element Inference	89
5.4.3	Multiplexer Inference	94
5.4.4	Three-State Inference	97
5.5	Order Dependency	98
5.5.1	Blocking versus Non-Blocking Assignments in Verilog	98
5.5.2	Signals versus Variables in VHDL	99
5.6	Chapter Summary	100
Chapter 6	Constraining Designs	101
6.1	Environment and Constraints	102
6.1.1	Design Environment	102
6.1.2	Design Constraints	107
6.2	Advanced Constraints	114
6.3	Clocking Issues	116
6.3.1	Pre-Layout	117
6.3.2	Post-Layout	118
6.3.3	Generated Clocks	119
6.4	Putting it Together	120
6.5	Chapter Summary	122
Chapter 7	Optimizing Designs	125
7.1	Design Space Exploration	125
7.2	Total Negative Slack	129
7.3	Compilation Strategies	131
7.3.1	Top-Down Hierarchical Compile	131
7.3.2	Time-Budgeting Compile	132
7.3.3	Compile-Characterize-Write-Script-Recompile	134
7.3.4	Design Budgeting	135
7.4	Resolving Multiple Instances	137
7.5	Optimization Techniques	139
7.5.1	Compiling the Design	139
7.5.2	Flattening and Structuring	141
7.5.3	Removing Hierarchy	144
7.5.4	Optimizing Clock Networks	145
7.5.5	Optimizing for Area	148
7.6	Chapter Summary	148
Chapter 8	Design for Test	151
8.1	Types of DFT	151
8.1.1	Memory and Logic BIST	152
8.1.2	Boundary Scan DFT	153
8.2	Scan Insertion	153
8.2.1	Shift and Capture Cycles	154
8.2.2	RTL Checking	157
8.2.3	Making Design Scannable	158
8.2.4	Existing Scan	161
8.2.5	Scan Chain Ordering	162
8.2.6	Test Pattern Generation	164
8.2.7	Putting it Together	165
8.3	DFT Guidelines	166
8.3.1	Tri-State Bus Contention	167
8.3.2	Latches	167
8.3.3	Gated Reset or Preset	167
8.3.4	Gated or Generated Clocks	168
8.3.5	Use Single Edge of the Clock	169
8.3.6	Multiple Clock Domains	169
8.3.7	Order Scan-Chains to Minimize Clock Skew	170
8.3.8	Logic Un-Scannable due to Memory Element	170
8.4	Chapter Summary	173
Chapter 9	Links to Layout & Post Layout OPT	175
9.1	Generating Netlist for Layout	177
9.1.1	Uniquify	177
9.1.2	Tailoring the Netlist for Layout	179
9.1.3	Remove Unconnected Ports	180
9.1.4	Visible Port Names	180
9.1.5	Verilog Specific Statements	181
9.1.6	Unintentional Clock or Reset Gating	182
9.1.7	Unresolved References	183
9.2	Layout	183
9.2.1	Floorplanning	183
9.2.2	Clock Tree Insertion	188
9.2.3	Transfer of Clock Tree to Design Compiler	192
9.2.4	Routing	194
9.2.5	Extraction	194
9.3	Post-Layout Optimization	199
9.3.1	Back Annotation and Custom Wire Loads	200
9.3.2	In-Place Optimization	202
9.3.3	Location Based Optimization	203
9.3.4	Fixing Hold-Time Violations	205
9.4	Chapter Summary	209
Chapter 10	Physical Synthesis	211
10.1	Initial Setup	212
10.1.1	Important Variables	212
10.2	Modes of Operation	213
10.2.1	RTL 2 Placed Gates	213
10.2.2	Gates to Placed Gates	216
10.3	Other PhyC Commands	220
10.4	Physical Compiler Issues	221
10.5	Back-End Flow	223
10.6	Chapter Summary	223
Chapter 11	SDF Generation	225
11.1	SDF File	226
11.2	SDF File Generation	228
11.2.1	Generating Pre-Layout SDF File	228
11.2.2	Generating Post-Layout SDF File	231
11.2.3	Issues Related to Timing Checks	232
11.2.4	False Delay Calculation Problem	233
11.2.5	Putting it Together	235
11.3	Chapter Summary	237
Chapter 12	Primetime Basics	239
12.1	Introduction	240
12.1.1	Invoking PT	240
12.1.2	PrimeTime Environment	240
12.1.3	Automatic Command Conversion	241
12.2	Tcl Basics	242
12.2.1	Command Substitution	243
12.2.2	Lists	243
12.2.3	Flow Control and Loops	245
12.3	PrimeTime Commands	245
12.3.1	Design Entry	245
12.3.2	Clock Specification	246
12.3.3	Timing Analysis Commands	250
12.3.4	Other Miscellaneous Commands	256
12.4	Chapter Summary	259
Chapter 13	Static Timing Analysis	261
13.1	Why Static Timing Analysis?	261
13.1.1	What to Analyze?	262
13.2	Timing Exceptions	263
13.2.1	Multicycle Paths	263
13.2.2	False Paths	267
13.3	Disabling Timing Arcs	270
13.3.1	Disabling Timing Arcs Individually	270
13.3.2	Case Analysis	272
13.4	Environment and Constraints	272
13.4.1	Operating Conditions--A Dilemma	273
13.5	Pre-Layout	274
13.5.1	Pre-Layout Clock Specification	275
13.5.2	Timing Analysis	276
13.6	Post-Layout	278
13.6.1	What to Back Annotate?	278
13.6.2	Post-Layout Clock Specification	279
13.6.3	Timing Analysis	280
13.7	Analyzing Reports	284
13.7.1	Pre-Layout Setup-Time Analysis Report	285
13.7.2	Pre-Layout Hold-Time Analysis Report	286
13.7.3	Post-Layout Setup-Time Analysis Report	289
13.7.4	Post-Layout Hold-Time Analysis Report	291
13.8	Advanced Analysis	292
13.8.1	Detailed Timing Report	293
13.8.2	Cell Swapping	296
13.8.3	Bottleneck Analysis	297
13.8.4	Clock Gating Checks	300
13.9	Chapter Summary	303
	Appendix A	306
	Appendix B	319
	Index	321