ESSCIRC 2004: Proceedings of the 30th European Solid-State Circuits Conference Leuven, Belgium, 2004, 21-23 September, 2004 Book

	On ambient intelligence, needful things and process technology	3
	Low power digital cicuit design	11
	Integrated circuits for the biology to silicon interface
	Low voltage and low power aspects of data converter design	29
	Technology considerations for automotive	37
	UWBFM : a low and medium data rate constant envelope UWB communications system with localization potential	45
	Assessment of the merits of CMOS technology scaling for analog circuit design	57
	DSP, a technology, a product, a revolution	65
	A wideband high-linearity RF receiver front-end in CMOS	71
	Silicon bipolar up and down-converters for 5 GHz WLAN applications	75
	An integrated low power CMOS baseband analog design for direct conversion receiver	79
	60 GHz transceiver circuits in SiGe:C BiCMOS technology	83
	L1/L2 dual-band CMOS GPS receiver	87
	2.4 GHz receiver for sensor applications	91
	A multi-continuously-tunable lowpass filter for zero-IF mobile applications	95
	Low-power widely tunable Gm-C filter with an adaptive DC blocking, triode-biased MOSFET transconductor	99
	A Gm-C baseband filter with automatic frequency tuning for a direct conversion IEEE802 wireless LAN receiver	103
	Temperature stabilized tunable Gm-C filter for very low frequencies	107
	A highly linear pseudo-differential transconductance	111
	A high-linear 160 MHz CMOS PGA	115
	Performance degradation of an LC-tank VCO by impact of digital switching noise	119
	A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators	123
	A harmonic quadrature LO generator using a 90[degree] delay-locked loop	127
	LC-oscillators above 100 GHz in silicon-based technology	131
	55 GHz CMOS frequency divider with 3.2 GHz locking range	135
	A wideband CMOS VCO for zero-IF GSM-CDMA single-chip transceiver	139
	Transconductance with capacitances feedback compensation for multistage amplifiers	143
	A 0.5 V bulk-input fully differential operational transconductance amplifier	147
	A 14 V high speed driver in 5 V only 0.35 [mu]m standard CMOS	151
	A 0.22 mm[superscript 2] 7.25 mW per-channel audio stereo-DAC with 97 dB-DR and 39 dB SNRout	155
	A digital modulator with bandpass delta-sigma modulator	159
	Low-power 14-bit current steering DAC for ADSL 2+/CO applications in 0.13 [mu]m CMOS	163
	A 14 bit 130 MHz CMOS current-steering DAC with adjustable INL	167
	A power cut-off technique for gate leakage suppression	171
	Efficiency of body biasing in 90 nm CMOS for low power digital circuits	175
	Charge recycling sense amplifier based logic : securing low power security IC's against DPA	179
	A 3 mW continuous-time E[Delta]-modulator for EDGE/GSM with high adjacent channel tolerance	183
	A Sigma-Delta modulator with bitstream-controlled dynamic element matching	187
	A 120 dB 300 mW stereo audio A/D converter with 110 dB THD+N	191
	A 48-860 MHz TV splitter amplifier exhibiting an IIP2 and IIP3 of 94 dBmV and 73 dBmV	195
	A 5.0 mW 0dB FSK transmitter for 315/433 MHz ISM applications in 0.25 [mu]m CMOS	199
	A 5.2 GHz silicon bipolar power amplifier for IEEE 802.11a and HIPERLAN2 wireless LANs	203
	4 Mb MOSFET-selected phase-change memory experimental chip
	Variability analysis for sub-100 nm PD/SOICMOS SRAM cell	211
	A high density, low leakage, 5T SRAM for embedded caches	215
	The impact of random doping effects on CMOS SRAM cell	219
	A 2.4 GHz bandwidth OEIC with voltage-up-converter	223
	Ultra high-compliance CMOS current mirrors for low voltage charge pumps and references	227
	Power-efficient super class AB OTAs	231
	A CMOS V-I converter with 75 dB SFDR and 360 [mu]W power consumption	235
	1.5 GHz opamp in 120 nm digital CMOS architectures	239
	Thermally optimized demagnetization of inductive loads	243
	A 97mW 110MS/s pipeline ADC implemented in a 0.18 [mu]m digital CMOS	247
	A 0.11 mm[superscript 2] low-power A/D-converter cell for 10b 10 MS/s operation	251
	A 2.7 mW 1 MPSps 10b analog-to-digital converter with built-in reference buffer and 1 LSB accuracy programmable input ranges	255
	A configurable time-interleaved pipeline ADC for multi-standard wireless receivers	259
	A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end	263
	Optical receiver IC for CD/DVD/blue-laser applications	267
	Design of low noise CMOS OEIC for blu-ray disc optical storage systems	271
	Two high-speed optical front-ends with integrated photodiodes in standard 0.18 [mu]m CMOS	275
	5 Gbps 0.35 [mu]m CMOS driver for laser diode or optical modulator	279
	Burst-mode transmitter for 1.25 Gbs/s Ethernet PON applications	283
	An inductor-based 52 GHz 0.18 [mu]m SiGe HBT cascode LNA with 22 dB gain	287
	A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS
	A 5 GHz low-noise amplifier with inductive ESD protection exeeding 3 kV HBM	295
	A digital CMOS micro-hotplate array for analysis of environmentally relevant gases	299
	VLSI implementation of the sphere decoding algorithm	303
	Towards AES crypto-chip resistant to different power analysis	307
	A delay-encoding-logic array processor for dynamic programming matching	311
	A power-efficient 4-PAM signaling scheme with conventional encoder in space for chip-to-chip communication	315
	Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC	319
	Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity	323
	On-chip versus off-chip passives in multi-band radio design	327
	A mixed-signal integrated circuit for FM-DCSK modulation	331
	Design of a highly integrated tuner suitable for analog and digital TV systems	335
	A 6bit, 1.2 GSps low-pwer flash-ADC in 0.13 [mu]m digital CMOS	339
	A 1.GS/s, 16 times interleaved track and hold with 7.6 ENOB in 0.12 [mu]m CMOS	343
	4 GB/s track and hold circuit using parasitic capacitance canceller	347
	A cavity channel SESO embedded memory with low standby-power techniques	351
	High-bit-rate low-power decision circuit using InP/InGaAs HBT technology	355
	1-58 Gb/s PRBS generator with <1.1>ps RMS jitter in InP technology	359
	A 10 GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator	363
	A 10 GHz frequency synthesizer for 802.11a in 0.18 [mu]m CMOS	367
	A low jitter triple-band digital LC PLL in 130 nm CMOS	371
	A 0.8-8 GHz 9.7mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator	375
	Digital delay locked loop with open-loop digital cycle corrector for 1.2 GHz/s/pin double data rate SDRAM	379
	A small ripple regulated charge pump with automatic pumping control schemes	383
	A mixed-signal chip with HV-protected plus in 0.35 [mu]m based HV technology	387
	Temperature referenced supply voltage and forward-body bias control (TSFC) architecture for minimum power consumption	391
	A low-power clock generator for system-on-chip (SoC) processors	395
	A novel active feedback flyback	399
	Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuit	403
	Quadrature oscillator with pre-distorted waveforms for application in MEMS-based mechanical spectrum analyzer	407
	High-sensitivity, high-dynamic range 768x576 pixel CMOS image sensor	411
	A colour 3200 fps high-speed CMOS imager for endoscopy in bio-medical applications	415