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Verilog for Digital Design Book

Verilog for Digital Design
Verilog for Digital Design, * Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language
* Verilog is a hardware description language us, Verilog for Digital Design has a rating of 3 stars
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Verilog for Digital Design, * Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language * Verilog is a hardware description language us, Verilog for Digital Design
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  • Verilog for Digital Design
  • Written by author Frank Vahid
  • Published by Wiley, John & Sons, Incorporated, July 2007
  • * Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language * Verilog is a hardware description language us
  • * Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language * Verilog is a hardware description language us
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Authors

Preface     vii
To Those About to Study Verilog     vii
To Teachers of Verilog     vii
About the Book     ix
Chapter Overview     ix
Accompanying Resources     ix
Formatting     x
Acknowledgments     x
About the Authors     x
Contents     xiii
Introduction     1
Digital Systems     1
Hardware Description Languages     2
HDLs for Design and Synthesis     6
Combinational Logic Design     9
AND, OR, and NOT Gates     9
Modules and Ports     9
Module Procedures-always     11
Simulation and Testbenches-A First Look     13
Variables and nets     15
Module procedures-initial     15
Delay control     16
Comments     17
Combinational Circuit Structure     18
Module Instantiations     18
Port Connections     20
Simulating The Circuit     21
Top-Down Design-Combinational Behavior to Structure     23
Procedures with If-Else Statements     25
Multiple Module Descriptions for One Module     28
Common Pitfalls     29
Missing inputs from event control expression     29
Outputs not assigned on every pass     30
Hierarchical Circuits     32
Using Modules as Instances     32
Built-In Logic Gates     34
Sequential Logic Design     35
Register Behavior     35
Vectors     35
Constant Numbers     37
Synchronous Storage Using a reg Variable     37
Testbenches with Clocks     38
Common Pitfalls     40
Using an always procedure instead of an initial procedure     40
Not including any delay control or event control in an always procedure     40
Not initializing all input ports     41
Not declaring an identifier used in a port connection     42
Finite-State Machines (FSMs)-Sequential Behavior     43
Multiple Always Procedures and Shared Variables     43
Parameters (Constants)     44
Procedures with Case Statements     44
Self-Checking Testbenches     46
Top-Down Design-FSMs to Controller Structure     49
Common Pitfall     51
Not assigning outputs in every state     51
More Simulation Concepts     53
The Simulation Cycle     53
Scheduled Events     56
Resets     59
Describing Safe FSMs     62
Datapath Components     65
Multifunction Registers     65
Continuous Assignment Statement     66
Common Pitfall     68
Not using a begin-end block with every if statement     68
Adders     69
Built-In Arithmetic Operations     69
Concatenation     72
Blocking Versus Non-Blocking Assignments     72
Left-Side Concatenation     73
Shift Registers     74
Procedures with For Loop Statements     76
Integer Variables     77
Relational, Logical, and Equality Operators     78
File Input and Output     79
Functions and tasks     80
File input and output procedures     81
While loops     82
Common Pitfall     83
Creating a loop that cannot be unrolled during synthesis     83
Comparators     85
Unsigned and Signed Numbers     85
Common Pitfall     87
Unintentional use of one of Verilog's many automatic conversions      87
Register Files     88
Using High-Impedance Values     90
Conditional Operator "?"     91
Multiple Drivers of One Net     93
Arrays     95
Common Pitfall     96
Confusing bitwise and logical operators     96
Register-Transfer Level (RTL) Design     97
High-Level State Machine (HLSM) Behavior     97
Top-Down Design-HLSM to Controller and Datapath     102
Describing a State Machine using One Procedure     109
Improving Timing Realism     112
Delay Control on Right Side of Assignment Statements     112
Algorithmic-Level Behavior     114
Top-Down Design-Converting Algorithmic-Level Behavior to RTL     119
Automated Synthesis from the Algorithmic-Level     122
Simulation Speed     122
Memory     123
Verilog Mini-Reference     129
Basic Syntax     129
Comments     129
Identifiers     130
Keywords     130
Numbers     131
Integer Constant     131
Real Constant     133
Strings     133
Declarations     134
Net (Wire)      134
Module     134
Ports     134
Parameter     135
Local Parameter     136
Variable (Reg)     137
Statements     137
Assignment Statement     137
Blocking Assignment     137
Non-blocking Assignment     138
Continuous Assignment     138
Case Statement     139
If-Else Statement     141
Loop Statement     142
For Loop     142
Repeat Loop     143
While Loop     143
Null     144
Procedure     144
Always Procedure     144
Initial Procedure     146
Module Instantiation     146
Port Connection     147
Parameter Assignment     147
Timing control     148
Delay Control     148
Event Control     149
Timescale Directive     149
Wait Statement     150
Operators     150
Arithmetic     150
Bitwise     151
Concatenation     151
Conditional     152
Equality      152
Logical     153
Reduction     153
Relational     154
Shift     154
Operator Precedence     155
System Tasks and Functions     155
{dollar}display and {dollar}write     156
File Input and Output     157
{dollar}fopen     157
{dollar}feof     157
{dollar}fgetc     158
{dollar}fclose     158
{dollar}fdisplay and {dollar}fwrite     158
{dollar}readmemb and {dollar}readmemh     158
{dollar}signed and {dollar}unsigned     159
{dollar}time     159
Common Data Types     159
Array     159
Integer     160
Signed     160
Vector     160
Index     163


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Verilog for Digital Design, * Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language
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Verilog for Digital Design, * Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language
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