Digital Design Book

Preface     ix
Digital Systems and Binary Numbers     1
Digital Systems     1
Binary Numbers     3
Number-Base Conversions     5
Octal and Hexadecimal Numbers     8
Complements     9
Signed Binary Numbers     14
Binary Codes     17
Binary Storage and Registers     25
Binary Logic     28
Boolean Algebra and Logic Gates     36
Introduction     36
Basic Definitions     36
Axiomatic Definition of Boolean Algebra     38
Basic Theorems and Properties of Boolean Algebra     41
Boolean Functions     44
Canonical and Standard Forms     48
Other Logic Operations     55
Digital Logic Gates     57
Integrated Circuits     63
Gate-Level Minimization     70
Introduction     70
The Map Method     70
Four-Variable Map     76
Five-Variable Map     81
Product-of-Sums Simplification     83
Don't-Care Conditions     86
NAND and NOR Implementation     89
Other Two-Level Implementations     96
Exclusive-OR Function     101
Hardware Description Language     106
Combinational Logic     122
Introduction     122
Combinational Circuits     122
Analysis Procedure     123
Design Procedure     126
Binary Adder-Subtractor     130
Decimal Adder     139
Binary Multiplier     142
Magnitude Comparator     144
Decoders     146
Encoders     150
Multiplexers     152
HDL Models of Combinational Circuits     159
Synchronous Sequential Logic     182
Introduction     182
Sequential Circuits     182
Storage Elements: Latches     184
Storage Elements: Flip-Flops     188
Analysis of Clocked Sequential Circuits     195
Synthesizable HDL Models of Sequential Circuits     207
State Reduction and Assignment     227
Design Procedure     225
Registers and Counters     242
Registers     242
Shift Registers     245
Ripple Counters     253
Synchronous Counters     258
Other Counters      265
HDL for Registers and Counters     269
Memory and Programmable Logic     284
Introduction     284
Random-Access Memory     285
Memory Decoding     291
Error Detection and Correction     296
Read-Only Memory     299
Programmable Logic Array     305
Programmable Array Logic     309
Sequential Programmable Devices     311
Design at the Register Transfer Level     334
Introduction     334
Register Transfer Level (RTL) Notation     334
Register Transfer Level in HDL     336
Algorithmic State Machines (ASMs)     345
Design Example     352
HDL Description of Design Example     367
Sequential Binary Multiplier     371
Control Logic     376
HDL Description of Binary Multiplier     382
Design with Multiplexers     390
Race-Free Design     407
Latch-Free Design     403
Other Language Features     404
Asynchronous Sequential Logic     415
Introduction     415
Analysis Procedure     477
Circuits with Latches     425
Design Procedure     433
Reduction of State and Flow Tables     439
Race-Free State Assignment     446
Hazards     452
Design Example     457
Digital Integrated Circuits     471
Introduction     471
Special Characteristics     473
Bipolar-Transistor Characteristics     477
RTL and DTL Circuits     481
Transistor-Transistor Logic     484
Emitter-Coupled Logic     493
Metal-Oxide Semiconductor     495
Complementary MOS     498
CMOS Transmission Gate Circuits     501
Switch-Level Modeling with HDL     505
Laboratory Experiments with Standard ICs and FPGAs 57     511
Introduction to Experiments     511
Experiment 1: Binary and Decimal Numbers     516
Experiment 2: Digital Logic Gates     579
Experiment 3: Simplification of Boolean Functions     520
Experiment 4: Combinational Circuits     522
Experiment 5: Code Converters     524
Experiment 6: Design with Multiplexers     526
Experiment 7: Adders and Subtractors     527
Experiment 8: Flip-Flops     550
Experiment 9: Sequential Circuits     532
Experiment 10: Counters     534
Experiment 11: Shift Registers     535
Experiment 12: Serial Addition     538
Experiment 13: Memory Unit     539
Experiment 14: Lamp Handball     547
Experiment 15: Clock-Pulse Generator     545
Experiment 16: Parallel Adder and Accumulator     547
Experiment 17: Binary Multiplier     549
Experiment 18: Asynchronous Sequential Circuits     553
Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs     553
Standard Graphic Symbols     589
Rectangular-Shape Symbols     559
Qualifying Symbols     562
Dependency Notation     564
Symbols for Combinational Elements     566
Symbols for Flip-Flops     550
Symbols for Registers     570
Symbols for Counters     573
Symbol for RAM     575
Answers to Selected Problems     577
Index     597